(Solved):   1. Design and analyses a microcontroller instruction cycle pipeline to execute an embedded ...

 

1. Design and analyses a microcontroller instruction cycle pipeline to execute an embedded program which has 100 instructions. Each instruction has a uniform period and has 5 pipeline stages in the following order Instruction Fetch (IF), Instruction Decode (ID), Execute (Ex), Memory Access (MEM) and Register Write Back (WB). The fetch operation takes 3 clock cycles, decode operation takes 2 clock cycles, execution operation takes 4 cycles, memory access takes 3 cycles and register write back takes 2 cycles. a) With necessary diagrams, calculate the total number of clock cycles that will take to execute the program. b) If the microcontroller is given a clock with input clock frequency 2 GHz, what is the maximum clock frequency with which the microcontroller can operate? c) If the instruction pipeline is flushed after every 40 instructions, calculate the total number of clock cycles taken. d) In order to increase the microcontroller operating frequency, a register is placed in between the pipeline. Where it should be placed, and after placing, what is the new maximum operating frequency, and total number of clocks cycles the program will take without pipeline flushing?